1. Field of the Invention
The present invention relates to a memory apparatus and a data processor using the same, and, more particularly, it relates to a memory apparatus and a data processor using the same capable of generating a contiguous word address automatically from a word address which is to be accessed originally, when accessing a memory across a word boundary.
2. Description of the Related Art
Generally speaking, a memory apparatus is constituted by, a memory body (hereinafter, merely referred to as a memory), a decoder which decodes an address signal inputted from the outside of the memory apparatus for designating an address to be accessed, a sense amplifier for amplifying a data signal read from the memory so as to output to the outside of the memory apparatus, and a driver which drives a data signal given from the outside when writing data to memory and so on.
Now, there is a case where the address of one-bit unit or the bit address is granted to the memory, or a case where the address of one-word unit or the word address is granted, or a case where the both are granted. When accessing such memory to which the word address is granted, there is a case where, depending on the instruction and data, two words of the original address and its contiguous word are accessed at a time, and furthermore, when accessing the memory capable of storing one-word-length data across a word boundary, the two contiguous words must be accessed together.
Conventionally, the memory apparatus, wherein the one-word-length data can be arranged on the memory across the word boundary, is constituted as shown in a block diagram of FIG. 1.
A main storage 1001 as the memory is connected to a main storage access unit 1002 via an address bus 1003 and a data bus 1004, and word data on the main storage 1001 designated by an address signal given via the address bus 1003 is outputted to the data bus 1004. Inside of one word in the main storage 1001 is allocated to in-word addresses 0 to n, and a memory access request outputted from the main storage access unit 1002 is available only in a word unit. And, when accessing the one-word-length data whose word address starts from W.sub.1, and in-word address starts from W.sub.0, the address W.sub.1 of all submemories 1005, 1006, 1007 are accessed by submemory address buses 1008, 1009, 1010, and data m.sub.0, m.sub.1, m.sub.2 are read and written via submemory data buses 1011, 1012, 1013.
At this time, when the in-word address W.sub.0 is other than zero, the main storage access unit 1002 judges it and a next word address W.sub.1 +1 is also accessed in a same manner. Two one-word data accessed in the manner described above are composed in the main storage access unit 1002, thereby to obtain a desired one-word data.
However, in the conventional configuration as described above, in case only reading and writing of the one-word-length data of any address is required, since the memory access is always performed twice when the data extends over two words on the main storage 1001, the memory access takes a long time.
From such circumstances, the invention disclosed in, for example, Japanese Patent Application Laid-Open No. 2-244350 (1990) , has been proposed. The invention disclosed in Japanese Patent Application Laid-Open No. 2-244350 (1990) has its configuration shown in a block diagram of FIG. 2. In FIG. 2, numeral 1014 designates a main storage capable of storing one-word-length data across the word boundary, and connected to a main storage access unit 1015 and an in-word location exchange circuit 1019 via an address bus 1016 and a data bus 1017. The main storage 1014 is composed by n+1 units of submemories (M.sub.0, M.sub.1 . . . Mn) 1020, 1021, 1022 and a word select address generating circuit 1018.
Access to the submemories 1020, 1021, 1022 is conducted independently for the submemory address buses 1023, 1024, 1025 and for the submemory data buses 1026, 1027, 1028 respectively, respective access data values being designated as m.sub.0, m.sub.1 . . . m.sub.n. The word select address generating circuit 1018 receives as inputs a word select address bus 1029 indicating a word address in the address bus 1016 and an in-word select address bus 1030 indicating an in-word address, and generates the submemory to be accessed and its word select address according to an operation table shown in FIG. 3, from respective values W.sub.1 and W.sub.0 of the word address and the in-word address, and outputs to the submemory address buses 1023, 1024, 1025.
Meanwhile, the in-word location exchange circuit 1019 receives as an input an in-word select address bus 1031 indicating the in-word address, rearranges order of data m.sub.0, m.sub.1, m.sub.2 corresponding to the submemory data buses 1026, 1027, 1028 of the data bus 1017 from the in-word address value W.sub.0 so as to align them, according to an operation table shown in FIG. 4.
By the configuration as described above, the main storage 1014, when reading one-word-length data from the address W.sub.0 indicated by the in-word select address bus 1030 in the word address W.sub.1 indicated by the word select address bus 1029, responsive to the access request from the main storage access unit 1015 connected through the address bus 1016, reads submemory data from the W.sub.0 -th to n-th in-word address of the word address W.sub.1, and submemory data from the 0-th to (W.sub.0 -1)-th in-word address of the word address W.sub.1 +1 by one access.
Meanwhile, the data m.sub.0, m.sub.1 . . . mn thus read out are transferred to the in-word location exchange circuit 1019 by one bus cycle, rearranged into the one-word-length data in order of m.sub.W0, . . . m.sub.n, m.sub.0 . . . mw.sub.w0-1, and sent to the main storage access unit 1015.
The writing operation of such one-word-length data is similar to the aforementioned reading operation.
As a similar art, the invention disclosed in Japanese Patent Application Laid-Open No. 2-255929 (1990) is known. The invention of the Japanese Patent Application Laid-Open No. 2-255929 (1990), frankly speaking, adopts a configuration including an adder for supplying the word address next to the word address at a start position of the data to be accessed from a (IPU, when it is indicated by the data length and data position to be accessed that the access extends over the word boundary.
As such, in the above-mentioned invention of the Japanese Patent Application Laid-Open No. 2-255929 (1990), the adder for giving the address to be accessed to the memory apparatus across the word boundary is included.
Meanwhile, in the aforementioned invention of the Japanese Patent Application Laid-Open No. 2-244350 (1990), though generating means (corresponding to the above-mentioned adder) of the contiguous word address is not defined, it is believed that substantially the same configuration is premised. Its ground is that, word lines which give the output of the word select address generating circuit (numeral 1018 in FIG. 2) respectively to the submemories are independent for respective submemories. Thus, it is clear that it is so constituted that, both the start portion address of the word to be accessed and the contiguous word address are prepared in the word select address generating circuit beforehand and are given to the submemories.
Now, since the memory is allowed to be accessed across the word boundary, when the configuration as shown in the conventional example is adopted, the following problems are encountered.
In order to generate the contiguous word address, an adder (or an incrementer) and a selector circuit for selecting either an input or an add result of the adder must be included. And hence, the amount of hardwares increases, and furthermore, since add processing has to be executed in the process of deciding an output value of the word select line to be given, practically, to the memory after the start address to be accessed is decided, the memory access time is considerably elongated.
Since the different addresses or word select lines must be provided independently for the respective submemories, the amount of hardwares is increased.
Since electric power consumption increases due to the reasons described above, in particular, such memory systems are not suitable for battery-driven-type processors.